############################################################################## # Class: TMbsMappingTofPar # Context: TestDefaultContext ############################################################################## [TMbsMappingTofPar] //---------------------------------------------------------------------------- // Switch ON/OFF debug tests, output & histos in mapping MappingDebug: Int_t 1 //---------------------------------------------------------------------------- // => If mapping detector channel for each TDC channel // Nb of TDC mapped (1) NbMappedTdc: Int_t 10 // Nb of channels per TDC (2) // Number of entries HAS TO match the number of TDCs in (1) // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NbChanTdc: Int_t \ 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 \ 32 32 32 32 32 32 // 32 32 32 32 32 32 32 32 32 32 32 32 32 32 // TDC Unique ID (aka 1st channel rising edge ID) // Number of entries HAS TO match the number of TDCs in (1) // 0x10000000 = edge = edge, 0 = Rising, 1 = Falling // 0x0FFF0000 = Channel ID = TDC Channel index, always 0 here as first channel index! // 0x0000FFF0 = TDC ID = TDC index, 0-4096 // 0x0000000F = TDC type = cf TofTdcDef.h, 1 = Caen, 2 = VFTX, 3 = TRB3, 4 = GET4 // 0 1 2 3 4 5 6 7 8 9 10 11 TdcUniqueId: Int_t \ 0x00000003 0x00000013 0x00000023 0x00000033 0x00000043 0x00000053 0x00000063 0x00000073 \ 0x00000083 0x00000093 // 0x00000273 0x00000283 0x00000293 0x000002A3 0x000002B3 0x000002C3 0x000002D3 => Spare addresses for FEE-TDC1 // 0x00000013 0x00000053 0x00000093 0x000000D3 0x00000113 => 2nd TRB3 TDC = BAD => Unused // List of all addresses in order: 4*4 TRB3, 19 FEE-TDC1, 3 spare FEE-TDC1, 4 reserved FEE-TDC1 addresses //0x00000003 0x00000013 0x00000023 0x00000033 0x00000043 0x00000053 0x00000063 0x00000073 \ //0x00000083 0x00000093 0x000000A3 0x000000B3 0x000000C3 0x000000D3 0x000000E3 0x000000F3 \ //0x00000103 0x00000113 0x00000123 0x00000133 0x00000143 0x00000153 0x00000163 0x00000173 \ //0x00000183 0x00000193 0x000001A3 0x000001B3 0x000001C3 0x000001D3 0x000001E3 0x000001F3 \ //0x00000203 0x00000213 0x00000223 0x00000233 0x00000243 0x00000253 0x00000263 0x00000273 \ //0x00000283 0x00000293 0x000002A3 0x000002B3 0x000002C3 0x000002D3 // TDC to Detector Mapping: for each tdc channel provides the Detector Unique ID to use // Formatting: 1 line per TDC, total nb of entries has to match the sum of (2) // Use 0xFFFFFFFF for unassigned channels // Detectors Unique ID // 0xFF000000 = Channel ID = 0 for 1st channel 1st side // 0x00800000 = Channel Side = 0 for 1st channel 1st side // 0x007F0000 = RPC ID = or detector ID // 0x0000F000 = SM Type = e.g. 0 for HD, 1 for Buc, 2 for plastics, 3 for Pad CRPC, 4 for reference signal 1 & 2, 5 for HD Big RPC, 6 for Buc multiple... // 0x00000FF0 = SM ID = e.g. 0 for HD, 1 for Buc, 2 for plastics, 3 for Pad CRPC, 4 for reference signal 1 & 2, 5 for HD Big RPC, 6 for Buc multiple ... // 0x0000000F = System ID = always 6 for TOF // e.g: 1st Ch left Buc RPC = 0x00001016, 1st ch left HD RPC = 0x00000006, 1st plastic left = 0x00002026, 2nd plastic left = 0x00012026, Reference = 0x00004046 // HD BUC PLA CRPC Ref BHD newBUC //const Int_t TMbsMappingTofPar::fgkiNbChDetType[7] = { 32, 72, 1, 8, 10, 56, 8 }; // SmType 0 1 2 3 4 5 6 7 8 9 10 // P3 Ref PLA P2 P5 Dia 2013 USTC TsgStr PAD 2012 // | | | | | | | | | | | // { 56, 72, 1, 32, 16, 1, 64, 16, 24, 48, 16 }; // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Mapping: Int_t \ 0x00003006 0x01003006 0x02003006 0x03003006 0x04003006 0x05003006 0x06003006 0x07003006 0x08003006 0x09003006 0x0A003006 0x0B003006 0x0C003006 0x0D003006 0x0E003006 0x0F003006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x10003006 0x11003006 0x12003006 0x13003006 0x14003006 0x15003006 0x16003006 0x17003006 0x18003006 0x19003006 0x1A003006 0x1B003006 0x1C003006 0x1D003006 0x1E003006 0x1F003006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x1F803006 0x1E803006 0x1D803006 0x1C803006 0x1B803006 0x1A803006 0x19803006 0x18803006 0x17803006 0x16803006 0x15803006 0x14803006 0x13803006 0x12803006 0x11803006 0x10803006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x0F803006 0x0E803006 0x0D803006 0x0C803006 0x0B803006 0x0A803006 0x09803006 0x08803006 0x07803006 0x06803006 0x05803006 0x04803006 0x03803006 0x02803006 0x01803006 0x00803006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x00804006 0x01804006 0x02804006 0x03804006 0x04804006 0x05804006 0x06804006 0x07804006 0x08804006 0x09804006 0x0A804006 0x0B804006 0x0C804006 0x0D804006 0x0E804006 0x0F804006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x0F004006 0x0E004006 0x0D004006 0x0C004006 0x0B004006 0x0A004006 0x09004006 0x08004006 0x07004006 0x06004006 0x05004006 0x04004006 0x03004006 0x02004006 0x01004006 0x00004006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x00002006 0x00802006 0x00002016 0x00802016 0x00002026 0x00802026 0x00002036 0x00802036 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x7FFFFFFF 0x00005026 0x01005026 0x02005026 0x03005026 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x00005006 0x01005006 0x02005006 0x03005006 0x04005006 0x05005006 0x06005006 0x07005006 0x08005006 0x09005006 0x0A005006 0x0B005006 0x0C005006 0x0D005006 0x0E005006 0x0F005006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ 0x00005016 0x01005016 0x02005016 0x03005016 0x04005016 0x05005016 0x06005016 0x07005016 0x08005016 0x09005016 0x0A005016 0x0B005016 0x0C005016 0x0D005016 0x0E005016 0x0F005016 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF //TSU Pad F01 - F04 //0x00009006 0x01009006 0x02009006 0x03009006 0x04009006 0x05009006 0x06009006 0x07009006 0x08009006 0x09009006 0x0A009006 0x0B009006 0x0C009006 0x0D009006 0x0E009006 0x0F009006 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF \ // Use extended Digis: Time and Tot stored as double // while "normal" digis rebin both to make them fit together in a single 32b integer UseExtDigi: Int_t 1 // Nb of Detectors mapped (3) NbMappedDet: Int_t 9 // Detectors Unique ID (aka 1st channel left side ID) // Number of entries HAS TO match the number of Detectors in (3) DetUniqueId: Int_t \ 0x00002006 0x00002016 0x00002026 0x00002036 0x00003006 0x00004006 0x00005006 0x00005016 0x00005026 ###########################